TAIPEI – Xilinx will sample this fall an FPGA that packs two million logic cells thanks to use of an emerging stacked silicon interconnect. The chip shows progress in so-called 2.5-generation silicon interposer techniques, but Xilinx and others cautioned many challenges are still ahead for making full 3-D stacks using through silicon vias (TSVs).
“What we have developed is just the beginning,” said Victor Peng, senior vice president of programmable platform development at Xilinx in a keynote talk at the 3-D IC Technology Forum, part of Semicon Taiwan here. “We believe in full 3-D ICs, but it will take longer and start with people who control anything everything in the chip stack,” said Peng.
TSMC aims to be one of the one-stop 3-D IC suppliers, and showed preliminary results on a complete TSV flow it hopes to have in place next year using copper interconnects. It expects integrated chip makers such as Intel and Samsung will also be early movers in the technology.
“If you can do end-to-end integration, the flow could be shorter and you could have better yields and reliability,” said Doug Chen-Hua Yu, senior director of interconnect and packaging R&D at TSMC.
For its part, Elpida said it has designed a 2 Gbit DRAM using two DDR3 x32 dice linked by about 880 TSVs. The device uses 80 percent less active power, half the standby power and is one-third the size of the two chips it replaces, making TSVs “really attractive for system design,” said Takayuki Watanabe, vice president of Elpida’s TSV packaging development group.
Earlier this year the company forged a partnership with Powertech Technology Inc, and UMC to build 3-D chips. The trio expect to serve three markets—mobile systems and high-end graphics and computers.
Chip stacks linking die at their edges using wirebonding have been around for cellphones and other products for years. The new work involves metal interconnects drilled into the dice to boost bandwidth.
“This involves much more than just another dimension of floor planning and place-and-route work,” said Peng of Xilinx. “If you just link die not meant to be stacked you will not have an optimal product,” he said.
“We need to rethink the architecture, and we are doing that thinking because we are looking at true 3-D FPGAs,” Peng added.
The Xilinx executive held up an early version of his upcoming FPGA for a packed crowd of about 500 engineers. It lays four Xilinx 7V2000T die slices side by side, connected by a 65nm silicon interposer using more than 20,000 micro-bumps with a latency of less than a nanosecond. The result is a 6.8 billion transistor chip that requires a whopping 45x45mm package.
“We are seeing a 3.5x increase in logic density with this technique, and you can match system level bandwidth to your needs while controlling power consumption,” Peng said. The chip runs at “tens of Watts” and requires “no exotic cooling,” he added.
Xilinx was able to use the stacking technology, in part because FPGA companies create their own design tools. Standard EDA tools for 3-D ICs are largely still in development.
“We are seeing a real uptick in interest in this technology and expect it could be adopted by applications we haven’t even thought of yet,” said Peng, in a brief interview with EE Times. “This is very compelling for communications designs that want to converge three or four existing FPGAs into one or for use in ASIC prototyping,” he said.