Price cited as top challenge in 3-D stacks

10/5/2011 Rick Merritt SANTA CLARA, Calif. – Major price reductions are needed for chip stacks using high density through-silicon vias (TSVs) before the technology can be used in high volume devices, said a Qualcomm engineering manager. Matt Nowak, a senior…


Rick Merritt

SANTA CLARA, Calif. – Major price reductions are needed for chip stacks using high density through-silicon vias (TSVs) before the technology can be used in high volume devices, said a Qualcomm engineering manager.

Matt Nowak, a senior director of advanced engineering at Qualcomm, reviewed progress on technology challenges for TSVs in a keynote address here. In comments after his talk, he said industry debates over prices and business models are the biggest hurdles ahead.

“TSVs are a long way off if we can’t solve the price problem,” said Nowak in discussion after his talk at the International Wafer-Level Packaging Conference here. “There’s a big gap between price and cost, a large delta” based on uncertainties and risks of a new technology and volume demand for it, he said.

Several sources say smartphone mobile applications processors could use TSVs as early as 2014, becoming one of the first high volume applications of the technology. A Wide I/O memory interface in the works at Jedec paired with TSVs aims to be the successor of a low power DDR3 link coming for next-generation mobile processors using a package-on package (PoP) approach.

“LPDDR3 is coming along as the next clear technology for package-on-package devices offering 12.8 Gbytes/second, and somewhere beyond that Wide I/O has the potential to intersect the market,” said Nowak who oversees work on TSVs at Qualcomm. “Technically Wide I/O could be used by 2014, but there are pricing and business model issues that if they are not settled will make it a moot point,” he added.

TSVs promise to raise performance while lowering power and keeping device sizes low for a range of applications including mobile processors.

“The Achilles heel [for TSVs] is cost,” Nowak said in his keynote. “Wide I/O DRAM is considerably more expensive than current PoP configurations, and PoP will continue to evolve and maybe find ways to squeeze one more generation out,” he said.

Nowak said one industry consortium, the EMC-3D group, recently concluded TSVs will add about $120 additional cost per wafer based on its models of tools now in production. The group claims on its Web site it sees a path to prices coming down to about an extra $150 per wafer.

The lack of clear business models complicates the pricing issue, Nowak said. For example, it’s still a matter of debate which parts of the process are done in a wafer fab and which in a packaging house and who will be liable for yields.

“Some companies may act as integrators and take liability–likely the model will evolve,” he said, noting that some TSV supply chain partnerships already are forming.

Motives and progress

Qualcomm designed a prototype 28nm TSV device in an effort to show both the promise and the problems with the technology.

“We are putting a lot of development work into this kind of technology,” said Nowak. “In a handheld you can’t dissipate more than about 3W, yet the ability to do things that drive a lot of power will be key differentiators,” he said.

More broadly, TSVs could help the semiconductor industry keep on its historic rate of offering a 30 percent cost reductions in transistors every year. Rising costs of lithography due in part to delays in extreme ultraviolet technology may challenge the industry to maintain that pace without TSVs, Nowak said.

The good news is engineers are making progress resolving or at least characterizing the technology challenges for building TSV stacks. “While there are many challenges still ahead, there’s an impressive body of knowledge being built up and that’s what we need,” he said.

He noted TSMC reported at the VLSI Symposium this year advances in creating a better dielectric liner for TSVs. Engineers have demonstrated in pilot lines vias with 10:1 aspect ratios, and mitigated problems of copper materials extruded outside the vias.

Nowak also cited progress in back-side wafer processing, temporary carriers for thinned wafers and demos of joining microbumps sometimes used instead of vias. EDA vendors have also made advances in both architectural tools to help explore design trade-offs and 2-D like authoring tools.

“You can design a category of useful devices with these tools,” he said.

Tools still lack standards for exchanging data on mechanical stresses and package and chip levels. Standards are also needed to define tolerances in electrostatic discharge levels which are being “drastically reduced” in TSVs, he said.

Test procedures are also still in development.

“It’s not clear if micro-probing will be used in volume products,” he said. “The whole point is to reduce tests, but we are still adding tests,” he said.

“In the end, I always come back to cost–that’s the challenge that determines how pervasive this technology will be in industry,” Nowak said.