Perfecting the 3-D chip

10/11/2011 R. Colin Johnson You’ve heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar. After almost a decade of major semiconductor engineering…


R. Colin Johnson

You’ve heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar. After almost a decade of major semiconductor engineering efforts worldwide aimed at making the structures manufacturable, three-dimensional ICs are poised for commercialization starting next year—several years behind schedule.

Chip makers have spent the past several years perfecting the through-silicon vias that will interconnect 3-D ICs. Now that TSVs have been honed for 2-D tasks, such as transferring data from the front side of a planar chip to bumps on the flip side, the stage is set for 3-D ICs using stacked dice.

Last winter’s International Solid-State Circuits Conference featured “almost-3-D” chips, such as Samsung’s much-publicized 1-Gbit mobile DRAM (with a planned ramp to 4 Gbits by 2013). Samsung’s 2.5-D technique mates stacked DRAM dice with TSVs and microbumps atop a system-in-package.

A second major 2.5-D success is expected this fall, when Xilinx promises to deliver a multi-FPGA solution using a packaging process that interconnects four side-by-side Virtex-7 FPGAs with microbumps on a silicon interposer. Taiwan Semiconductor Manufacturing Co. is making the silicon interposer, which redistributes the FPGAs’ interconnections using TSVs that mate to copper balls on a substrate package using a controlled-collapse chip connection (C4). TSMC promises to make its seminal 2.5-D-to-3-D transition technology available to its other foundry customers next year.

The surprise 3-D IC announcement for 2011, however, comes from IBM, which recently confided that it was already secretly mass-producing full-fledged 3-D ICs on high-volume mobile consumer devices, albeit using low-density TSVs. As a result of the experience it has gained, IBM now claims to have identified the remaining engineering hurdles to 3-D and says it expects to surmount them in 2012.

“The era of the one-trick pony is gone,” said Bernard Meyerson, vice president of research at IBM (Armonk, N.Y.). “You are not going to win the 3-D performance battle if you rely solely on materials, or chip architecture, or networking, or software and integration. To win at 3-D, you need to use all these resources together at the most holistic level possible.”

Last month, IBM announced it had approached 3M about creating a designer material—akin to asking for “a really tall short person,” as Meyerson described it—that would solve the last remaining engineering hurdle to 3-D ICs: overheating. 3M’s job is to create an underfill material that fits between stacked dice and is an electrical insulator (like a dielectric) but is more thermally conductive than silicon (like a metal). 3M promises to have its miracle material ready for commercialization in two years.

“Right now we have trials ongoing, and by 2013 we want to have a formula in place that is ready for widespread commercialization,” said Ming Cheng, technical director of 3M’s Electronics Markets Materials Division (see sidebar, last page).

Some analysts are not convinced the IBM-3M joint development effort will necessarily put the pair ahead in 3-D ICs.

“3M is making an underfill material that will address the thermal issues for 3-D stacking,” said Françoise von Trapp, principal analyst for advanced packaging technologies at the MEMS Investor Journal. “While that’s definitely one of the remaining limitations needing to be addressed before 3-D ICs go to volume production, I don’t think anyone believes it’s the final key to unlocking the remaining issues for 3-D stacks.”3-D everywhere

Even IBM’s claimed lead in 3-D IC production is not without its challengers. In fact, Tezzaron Semiconductor (Naperville, Ill.) has been offering 3-D IC design services for its tungsten TSV process for several years. Tezzaron’s FaStack process can create 3-D chips from heterogeneous dice on wafers as thin as 12 microns. It features wide I/O for stacked DRAMs with submicron interconnections as dense as 1 million TSVs per square millimeter.

Serial entrepreneur Zvi Or-Bach, a past winner of an EE Times ACE Award for Innovator of the Year, argues that 3-D IC designers need to move beyond TSVs to ultrahigh-density monolithic 3-D. That’s not a surprising view for Or-Bach, whose latest role is president and CEO of IP developer MonolithIC 3D Inc. (San Jose, Calif.). Startups like BeSang Inc. (Beaverton, Ore.) claim to be fabricating prototypes of TSV-free monolithic 3-D memory chips that could debut in 2012.

The state of the art today, however, is 3-D chip stacking using TSVs, and every major semiconductor company is working on the technology. “IBM is pushing the envelope, thinking beyond the current frame of things by partnering with 3M. However, every advance made by IBM in 3-D will unleash the creativity in competitors like Samsung, Intel and TSMC, all of which have independent development efforts under way for 3-D ICs,” said market watcher Richard Doherty, director of The Envisioneering Group (Seaford, N.Y.).

The techniques for making 3-D ICs are not new; rather, the current efforts focus on refining them. For instance, many CMOS imagers today use TSVs to bring pixel data from the front to the rear side of their substrate, and the idea of stacking chips itself dates back to early patents issued to transistor pioneer William Shockley circa 1958. Since then, many stacked-die configurations have been used—such as stacking a MEMS sensor atop an ASIC, or a small DRAM atop a processor core—but usually using wirebonding for interconnection.

Moving from wirebonds to TSVs allows interconnections to be denser. It also it frees designers from the tyranny of the rectangular “farm plot,” letting them design chip layouts more like circuit boards. Areas devoid of circuitry could be used for other structures, such as vertical interconnection buses or even chimneys for refrigerant gases. Heterogeneous 3-D stacked dice also offer a new level of integration, as whole systems can be combined into a single silicon brick.

“The most important thing that 3-D ICs bring is an opportunity to get away from the farm analogy, where every chip is divided up into adjoining rectangular neighborhoods that are fully populated,” said Doherty. “Instead of trying to use up all of the real estate on a chip, 3-D chip designers are going to start cutting out squares, triangles and circles [from dice] for vertical interconnect and to carry away heat.

“A lot of new ideas for chip design are being made possible by 3-D. Designers are going to have to think differently, since they can now mix their CPU, memory and I/O functions in novel ways that couldn’t be done when everything had to fit side-by-side on one postage stamp.”

The various semiconductor associations are all undertaking standards efforts for 3-D techniques. Semiconductor Equipment and Materials International has four groups working on 3-D IC standards. Its Three-Dimensional Stacked Integrated Circuits Standards Committee includes SEMI members Globalfoundries, Hewlett-Packard, IBM, Intel, Samsung and United Microelectronics Corp. (UMC), as well as Amkor, ASE, Europe’s Interuniversity Microelectronics Center (IMEC), Asia’s Industrial Technology Research Institute (ITRI), Olympus, Qualcomm, Semilab, Tokyo Electron and Xilinx.

Sematech, for its part, has established a 3-D Design Enablement Center. Participants include Altera, Analog Devices, LSI, ON Semiconductor and Qualcomm. Sematech also operates a 300-mm 3-D IC pilot line at the University of Albany’s College of Nanoscale Science and Engineering in New York state.

IMEC (Leuven, Belgium) is working with Cascade Microtech Inc. (Beaverton, Ore.) in the testing and characterization of 3-D ICs. And German research institute Fraunhofer IZM says it will be able to integrate processor, memory, logic, analog, MEMS and RF chips into monolithic 3-D ICs by 2014.

ITRI, based in Taiwan, sponsors a 3-D IC consortium that today has more than 20 members. Many of those participants are promising end-to-end 3-D IC foundry services starting as early as next year.

In September, at the 3-D IC Technology Forum held during Semicon Taiwan, Intel was reported to be working on stacked-die 3-D ICs (not to be confused with its FinFET trigate transistors, which are not intended for 3-D ICs). Also at Semicon, Elpida Memory (Tokyo) was reported to have made progress with Powertech Technology and UMC on a 2-Gbit DRAM that uses stacked DDR3 dice linked by high-density TSVs.

The Joint Electron Device Engineering Council is pioneering a Wide I/O standard for 3-D ICs that’s due by year’s end. The Jedec spec will support 512-bit-wide interfaces.

France’s CEA-Leti (Grenoble) is working with STMicroelectronics and silicon interposer maker Shinko Electric Industries Co. to smooth the 2.5-D to 3-D IC transition. The group is prototyping devices now at a 300-mm wafer fabrication facility and promises commercial designs as early as 2012.

Longer-range efforts are under way in Europe’s CMOSAIC program to find novel methods of cooling monolithic 3-D chip stacks beyond 2013. The four-year project involves IBM Zurich, École Polytechnique Fédérale de Lausanne (Paris) and the Swiss Federal Institute of Technology Zurich.

Sidebar: IBM, 3M pair off for 3-D

IBM + 3M = 3-D ICs. It’s a catchy formula. “Somewhere in the middle of those initials, 3M has the technology platforms to make 3-D work,” said Bernard Meyerson, vice president of research at IBM (Armonk, N.Y.)

After years of research into each of the component technologies needed to enable 3-D ICs, IBM decided there was a missing material so important that it cut a deal with 3M to create it. The key remaining obstacle to 3-D ICs, according to IBM, is an underfill material that can do double duty as an electrical insulator and a thermal conductor, wicking away heat from hot spots. IBM aims to use the material in conjunction with microfluidic channels containing refrigerants on 3-D structures.

“3M has the skills to meet the really disparate requirements for a 3-D IC adhesive,” said Meyerson. “You want infinite thermal conductivity in the adhesive, but you also want the electrical conductivity to be zero.”

The worst constraint, according to Meyerson, is that the coefficient of thermal expansion for the adhesive must match that of the metal used for the interconnect; otherwise, the adhesive will break the metallization when it heats up.

“Thermal conductivity, electrical conductivity and thermal expansion are all related, not to mention brittleness. It’s what we call an overconstrained system.”

Ming Cheng, technical director of 3M’s Electronics Markets Materials Division, said 3M “is essentially a materials company with the capability to tune the properties of adhesives and polymers to meet even these conflicting specifications. Our adhesive will be a combination of different types of polymers, oligomers and monomers, along with the necessary feelers and adhesion promoters that meet IBM’s specifications.”

According to 3M, it has not yet been decided whether the jointly developed 3-D IC adhesive will be sold to other chip makers. But in the past IBM has made a practice of licensing its key patents even to competitors.

3M also has experience with the fluids that are used today to cool hot spots in rack-mounted computers, and those fluids could soon flow through microfluidic channels cut into 3-D ICs. “Even if you have the perfect adhesive, it may be necessary to remove heat from the internal layers of a tall stack,” said Meyerson. “A microchannel-cooled radiator halfway through the stack could take out a bunch of heat from the middle of a silicon brick.”

Said Cheng: “Our Fluorinert electronic liquids are currently used to help cool equipment in data centers—mostly servers and hard drives—but with IBM we will also be exploring the liquids’ use to help cool 3-D ICs.”

Beyond perfecting the processing technologies to interconnect stacked dice and keep them cool, designers must consider the tide of data that will be streaming out of 3-D ICs, according to IBM. Photonics will become an integral part of 3-D ICs to handle the voluminous I/O.

“Electronic data transmission today can consume up to 50 percent of a chip’s power. Photonics is vastly more efficient in watts per bit and, for that reason, will be essential for 3-D ICs,” said Meyerson. “We’ll need lasers, modulators and detectors right in the 3-D IC stack.”

The work with IBM was announced just recently, but 3M has been working on 3-D solutions for some time. Earlier this year, in fact, 3M announced a technology for handling wafers destined for 3-D stacks. The company’s wafer-supporting-system (WSS) simplifies the handling of wafers that have been thinned for stacking.

WSS “first bonds the thin wafer to glass with a temporary adhesive so that the glass can support the wafer during bonding,” said Cheng. “After the two wafers are stacked, debonding allows the glass [carrier] to be removed.”

By 2013, 3M and IBM promise an end-to-end process ready for widespread high-volume commercialization of heterogeneous stacks of processor, memory, mixed-signal, networking and I/O chips formed into silicon skyscrapers as high as 100 chips per stack. — R. Colin Johnson