Harish Krishnaswamy, assistant professor of electrical engineering at Columbia Engineering, has generated a record amount of power output — by a power of five — using silicon-based nanoscale CMOS (complementary metal oxide semiconductor) technology for millimeter-wave power amplifiers. Power amplifiers are used in communications and sensor systems to boost power levels for reliable transmission of signals over long distances as required by the given application.
Krishnaswamy’s research will be reported at the June 2013 Institute of Electrical and Electronics Engineers Radio Frequency Integrated Circuits Symposium.
Used in virtually all forms of electronics around us, from phones to PCs, laptops, and tablets to satellite communications, nanoscale CMOS technologies have enabled the digital and communication revolution over the past 20 to 30 years. While nanoscale CMOS can do many things, Krishnaswamy explains the one thing that it cannot do very well is generate large amounts of power at high frequencies. This is because as transistors become smaller, they tend to break very easily with even a small amount of voltage or current — “they’re great for speed, but not power,” he notes. But generating large amounts of power at high frequencies is critical for communication over large distances with high bandwidth.
“We have devised a way to use multiple nanoscale CMOS transistors in carefully-aligned synchrony to ‘share the load’ and generate nearly a watt of power at millimeter-wave frequencies — nearly five times greater than what was currently possible,” says Krishnaswamy. “This could enable extremely high-bandwidth communication over extremely long distances for the first time.”
For instance, he points out, think of a citywide millimeter-wave wireless network that could support 10s of gigabit per second data rates — nearly two to three orders of magnitude higher than WiFi. Such a network could serve as the backbone infrastructure that enables extremely high-data-rate wireless links to mobile devices.
Krishnaswamy and his CoSMIC lab team accomplished this world record power output level for CMOS-based power amplifiers by developing a chip design methodology that stacks several nanoscale CMOS devices on top of each other so that they can handle larger voltages without compromising their speed. By stacking four 45 nanometer CMOS transistors within a power amplifier and then combining eight such amplifiers on a single chip, they achieved output power levels of nearly 0.5 W at 45 gigahertz.
“High-frequency nanoscale electronics is exciting to me because it is the confluence of many different aspects of science and engineering,” Krishnaswamy observes. “It’s an area where theory meets experimentation, where electro-magnetics meets chip and circuit design, and where the abstract meets real-life applications. I find it fascinating.”
The research was funded by DARPA MTO (Defense Advanced Research Projects Agency’s Microsystems Technology Office) through its ELASTx (Efficient Linearized All-Silicon Transmitter ICs) program.
Share this story on Facebook, Twitter, and Google:
Other social bookmarking and sharing tools:
The above story is reprinted from materials provided by Columbia University School of Engineering and Applied Science.
Note: Materials may be edited for content and length. For further information, please contact the source cited above.
Note: If no author is given, the source is cited instead.
Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.